EGGH95: Eurographics Workshop on Graphics Hardware 1995

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https://diglib.eg.org/handle/10.2312/340

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Browsing EGGH95: Eurographics Workshop on Graphics Hardware 1995 by Subject "graphics hardware"

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    An array based design for Real-Time Volume Rendering
    (The Eurographics Association, 1995) Doggett, Michael; W. Strasser
    This paper describes a new algorithm and hardware design for the generation of two dimensional images from volume data using the ray casting technique. The algorithm is part of an image generation system that is broken down into three subsystems. The first subsystem stores the input data in a buffered memory using a rearrangement of the original ad­ dress value. The second subsystem reads data points from the buffered memory and shifts the data to computational el­ ements in order to complete the viewing calculations for the image synthesis process. The final stage takes the results of the viewing calculations combined with the original input data to complete the surface rendering and pixel compositing to create the final image.This paper focusses on the second subsystem which con­ sists of two, two dimensional arrays of processing elements. The first array performs a limited angle, single dimension ro­ tation by shifting the data. The second array performs a two dimensional ray casting operation where viewing rays are as­ signed to each processing element. The first stage is outlined in this paper and the final rendering stages are the subject of previous work. The hardware design associated with these algorithms is described and tested. It is estimated that this ar­ chitecture is capable of producing 384 x 384 pixel images at speeds of 15 frames per second for 256 data sets. Real time generation of images of volume data is important in scientific applications of volume visualization and computer graphics applications which use volume graphics.
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    Hardware for Superior Texture Performance
    (The Eurographics Association, 1995) Knittel, G.; Schilling, A.; Kugler, A.; Straßer, W.; W. Strasser
    Mapping textures onto suIfaces of computer-gener­ ated objects is a technique which greatly improves the realism of their appearance. Unfortunately, this imposes high computational demands and, even worse, tremendous memory bandwidth require­ ments on the graphics system. Tight cost frames in the industry in conjunction with ever increasing user expectations make the design of a powerful texture mapping unit a difficult task.To meet these requirements we follow two different approaches. On the technology side, we observe a rapidly emerging technology which offers the com­ bination of enormous transfer rates and computing power: logic-embedded memories.On the algorithmic side, a common way to reduce data traffic is image compression. Its application to texture mapping, however, is difficult since the decompression must be done at pixel frequency.In this work we will focus on the latter approach, describing the use of a specific compression scheme for texture mapping. It allows the use of a very sim­ ple and fast decompression hardware, bringing high performance texture mapping to low-cost systems.
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    A pel-based Volume Rendering Accelerator
    (The Eurographics Association, 1995) Knittel, Günter; W. Strasser
    We discuss the underlying algorithms, design principles and implementation issues of an extremely compact and cost-efficient volume rendering accelerator for PCI-based systems. It operates on classified and shaded data sets which have been coded and compressed usingRedundant Block Compression (RBC), a tech­ nique originating from 2D-imaging and extended to 3D. This specific encoding scheme reduces drastically the required data traffic between the volume memory and the processing units. Thus, the volume data set can be placed into the main memory of the host, eliminating the need of a separate volume memory. Fur­ thermore, the tri-Iinear interpolation needed for perspective raycasting is very much simpli­ fied for RBC-transformed data sets.All in all, these techniques allow a volume ren­ dering accelerator to be implemented as a sin­ gle-chip coprocessor, or as an FPGA-based prototype for monochrome data sets as pre­ sented in this work. Although using a lossy compression scheme, image quality is still high, and expected frame rates are between 2 and 5Hz for typical data sets of 2563 voxels.