Systolic Architecture for Boolean Operations on Polygons and Polyhedra

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dc.contributor.authorKrishnan, D.en_US
dc.contributor.authorPatnaik, L.M.en_US
dc.date.accessioned2014-10-21T05:37:38Z
dc.date.available2014-10-21T05:37:38Z
dc.date.issued1987en_US
dc.description.abstractIn Computer-Aided Design applications there is often a need to compute the union, intersection and Merence of two polygons or polyhedra. The sequential algorithms for this problem are characterized by poor speed of response and large computational complexity. In order to remove these defects, an algorithm amenable to implementation on a parallel architecture is proposed. The parallel architecture designed is a systolic one which forms a dedicated subsystem to perform set-theoretic operations on polygons. The improvement in speed gained by using the systolic array as compared to a uniprocessor has been evaluated using simulation techniques. Extensions of this architecture to perform the same operations on polyhedra are also discussed.en_US
dc.description.number3en_US
dc.description.seriesinformationComputer Graphics Forumen_US
dc.description.volume6en_US
dc.identifier.doi10.1111/j.1467-8659.1987.tb00540.xen_US
dc.identifier.issn1467-8659en_US
dc.identifier.pages203-210en_US
dc.identifier.urihttps://doi.org/10.1111/j.1467-8659.1987.tb00540.xen_US
dc.publisherBlackwell Publishing Ltd and the Eurographics Associationen_US
dc.titleSystolic Architecture for Boolean Operations on Polygons and Polyhedraen_US
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