Mach-RT: A Many Chip Architecture for Ray Tracing

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dc.contributor.authorVasiou, Elenaen_US
dc.contributor.authorShkurko, Konstantinen_US
dc.contributor.authorBrunvand, Eriken_US
dc.contributor.authorYuksel, Cemen_US
dc.contributor.editorSteinberger, Markus and Foley, Timen_US
dc.date.accessioned2019-07-11T06:52:11Z
dc.date.available2019-07-11T06:52:11Z
dc.date.issued2019
dc.description.abstractWe propose an unconventional solution to high-performance ray tracing that combines a ray ordering scheme that minimizes access to the scene data with a large on-chip buffer acting as near-compute storage that is spread over multiple chips. We demonstrate the effectiveness of our approach by introducing Mach-RT (Many chip - Ray Tracing), a new hardware architecture for accelerating ray tracing. Extending the concept of dual streaming, we optimize the main memory accesses to a level that allows the same memory system to service multiple processor chips at the same time. While a multiple chip solution might seem to imply increased energy consumption as well, because of the reduced memory traffic we are able to demonstrate, performance increases while maintaining reasonable energy usage compared to academic and commercial architectures.en_US
dc.description.sectionheadersRay Tracing: Hardware and Performance
dc.description.seriesinformationHigh-Performance Graphics - Short Papers
dc.identifier.doi10.2312/hpg.20191188
dc.identifier.isbn978-3-03868-092-5
dc.identifier.issn2079-8687
dc.identifier.pages1-6
dc.identifier.urihttps://doi.org/10.2312/hpg.20191188
dc.identifier.urihttps://diglib.eg.org:443/handle/10.2312/hpg20191188
dc.publisherThe Eurographics Associationen_US
dc.subjectComputing methodologies
dc.subjectRay tracing
dc.subjectGraphics processors
dc.subjectComputer systems org.
dc.subjectParallel architectures
dc.titleMach-RT: A Many Chip Architecture for Ray Tracingen_US
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