An Architecture for a High Performance Rendering Engine

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dc.contributor.authorAckermann, Hans-Josefen_US
dc.contributor.authorHornung, Christophen_US
dc.contributor.editorA. Kaufmanen_US
dc.date.accessioned2014-02-06T14:15:19Z
dc.date.available2014-02-06T14:15:19Z
dc.date.issued1991en_US
dc.description.abstractWe present an architecture for a high-performance programmable rendering engine.This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texturemodulated and alpha-blended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms."en_US
dc.description.seriesinformationEurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn-en_US
dc.identifier.issn-en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH91/157-174en_US
dc.publisherThe Eurographics Associationen_US
dc.titleAn Architecture for a High Performance Rendering Engineen_US
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EGGH91: Eurographics Workshop on Graphics Hardware 1991