Compacted CPU/GPU Data Compression via Modified Virtual Address Translation

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dc.contributor.authorSeiler, Larryen_US
dc.contributor.authorLin, Daqien_US
dc.contributor.authorYuksel, Cemen_US
dc.contributor.editorYuksel, Cem and Membarth, Richard and Zordan, Victoren_US
dc.date.accessioned2020-10-30T18:18:28Z
dc.date.available2020-10-30T18:18:28Z
dc.date.issued2020
dc.description.abstractWe propose a method to reduce the footprint of compressed data by using modified virtual address translation to permit random access to the data. This extends our prior work on using page translation to perform automatic decompression and deswizzling upon accesses to fixed rate lossy or lossless compressed data. Our compaction method allows a virtual address space the size of the uncompressed data to be used to efficiently access variable-size blocks of compressed data. Compression and decompression take place between the first and second level caches, which allows fast access to uncompressed data in the first level cache and provides data compaction at all other levels of the memory hierarchy. This improves performance and reduces power relative to compressed but uncompacted data. An important property of our method is that compression, decompression, and reallocation are automatically managed by the new hardware without operating system intervention and without storing compression data in the page tables. As a result, although some changes are required in the page manager, it does not need to know the specific compression algorithm and can use a single memory allocation unit size. We tested our method with two sample CPU algorithms. When performing depth buffer occlusion tests, our method reduces the memory footprint by 3.1x. When rendering into textures, our method reduces the footprint by 1.69x before rendering and 1.63x after. In both cases, the power and cycle time are better than for uncompacted compressed data, and significantly better than for accessing uncompressed data.en_US
dc.description.number2
dc.description.sectionheadersHardware Architectures and Space Partitioning
dc.description.seriesinformationProceedings of the ACM on Computer Graphics and Interactive Techniques
dc.description.volume3
dc.identifier.doi10.1145/3406177
dc.identifier.issn2577-6193
dc.identifier.urihttps://doi.org/10.1145/3406177
dc.identifier.urihttps://diglib.eg.org:443/handle/10.1145/3406177
dc.publisherACMen_US
dc.subjectComputing methodologies
dc.subjectImage compression
dc.subjectGraphics processors
dc.subjectComputer systems organization
dc.subjectProcessors and memory architectures.
dc.subjectShared virtual memory
dc.subjectlossless compression
dc.subjectaddress swizzling
dc.subjectpage tables
dc.subjecttiled resources
dc.subjectsparse textures
dc.titleCompacted CPU/GPU Data Compression via Modified Virtual Address Translationen_US
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