A Scalable Architecture for Volume Rendering

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dc.contributor.authorKnittel, Günteren_US
dc.contributor.editorW. Strasseren_US
dc.date.accessioned2014-02-06T14:27:11Z
dc.date.available2014-02-06T14:27:11Z
dc.date.issued1994en_US
dc.description.abstractWe describe the operational principles of a scalable hardware accelerator for volume rendering. The basic philosophy is to provide an atomic unit which already provides sophisticated volume graphics at interactive rendering speed. Realtime speed can then be achieved by operating multiple units in par allel. The basic unit consists of just four VLSI chips and the volume memory and thus meets the requirements of a small size and low costs. Never theless it provides arbitrary perspective projections (e.g., for walk-throughs), Phong shading, a freely moveable light source, depth-cueing and interac tive, non-binary classification (semi-transparent display) at a frame rate of about 2.5Hz for 256 3 data sets.en_US
dc.description.seriesinformationEurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn-en_US
dc.identifier.issn-en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH94/058-069en_US
dc.publisherThe Eurographics Associationen_US
dc.titleA Scalable Architecture for Volume Renderingen_US
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EGGH94: Eurographics Workshop on Graphics Hardware 1994