Accommodating Memory Latency In A Low-cost Rasterizer

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dc.contributor.authorAnderson, Bruceen_US
dc.contributor.authorMacAulay, Roben_US
dc.contributor.authorStewart, Andyen_US
dc.contributor.authorWhitted, Turneren_US
dc.contributor.editorA. Kaufmann and W. Strasser and S. Molnar and B.-O. Schneideren_US
dc.date.accessioned2014-02-06T14:57:01Z
dc.date.available2014-02-06T14:57:01Z
dc.date.issued1997en_US
dc.description.abstractThis paper describes design tradeoffs in a very low cost rasterizer circuit targeted for use in a video game console. The greatest single factor affecting such a design is the character of memory to which the image generator is connected. Low costs generally constrain the memory dedicated to image generation to be a single package with a single set of address and data lines. While overall memory bandwidth determines the upper limit of performance in such a small image generator, memory latency has a far greater effect on the design. The use of Rambus memory provides more than enough aggregate bandwidth for a frame buffer as long as blocks of pixels are moved in each transfer, but its high latency can stall any processor not matched to the memory. The design described here utilizes a long pixel pipeline to match its internal processing latency to the external frame buffer memory latency.en_US
dc.description.seriesinformationSIGGRAPH/Eurographics Workshop on Graphics Hardwareen_US
dc.identifier.isbn0-89791-961-0en_US
dc.identifier.issn1727-3471en_US
dc.identifier.urihttps://doi.org/10.2312/EGGH/EGGH97/097-101en_US
dc.publisherThe Eurographics Associationen_US
dc.titleAccommodating Memory Latency In A Low-cost Rasterizeren_US
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EGGH97: SIGGRAPH/Eurographics Workshop on Graphics Hardware 1997