EGGH99: SIGGRAPH/Eurographics Workshop on Graphics Hardware 1999

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Adaptive Hierarchical Visibility in a Tiled Architecture
(The Eurographics Association, 1999) Xie, Feng; Shantz, Michael; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
This paper describes a method for occlusion culling in a tiled 3D graphics hardware architecture. Adaptive hierarchical visibility (AHV) is a simplified method for occlusion culling that is integrated into a tiled architecture for hardware rendering. AI-IV constructs a list of polygon bins for each tile where the bins are bucket sorted in order of increasing depth or Z. Polygon bins are rendered starting with the bin closest to the viewer. After some number of bins are rendered, a one layer, hierarchical Zbuffer (HZ) is constructed from the Z-buffer thus far accumulated for the rendered bins. Subsequent bins are rendered by first testing their polygons against the HZ to see if they are hidden. AHV is far simpler to implement in hardware and gives performance that matches or surpasses progressive hierarchical visibility (PHV) methods which update the HZ for each rendered pixel. Results show that AI-IV is superior on scenes with high depth complexity and small polygons. For tiles of widely ranging statistics, AHV competes surprisingly well with PHV. It offers dramatic performance improvement on low cost hardware for scenes of high depth complexity.
Antialiased Parameterized Solid Texturing Simplified for Consumer- Level Hardware Implementation
(The Eurographics Association, 1999) Hart, John C.; Carr, Nate; Karneya, Masaki; Tibbitts, Stephen A.; Coleman, Terrance J.; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
Procedural solid texturing was introduced fourteen years ago, but has yet to find its way into consumer level graphics hardware for teal-time operation. To this end, a new model is introduced that yields a parameterized function capable of synthesizing the most common procedural solid textures, specifically wood, marble, clouds and fire. This model is simple enough to be implemented in hardware, and can be realized in VLSI with as little as 100,000 gates. The new model also yields a new method for antialiasing synthesized textures. An expression for the necessary box filter width is derived as a function of the texturing parameters, the texture coordinates and the rasterization variables. Given this filter width, a technique for efficiently box filtering the synthesized texture by either mip mapping the color table or using a summed area color table are presented. Examples of the antialiased results are shown.
Fast Footprint MlPmapping
(The Eurographics Association, 1999) Hüttner, Tobias; Straßer, Wolfgang; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
Mapping textures onto surfaces of computer-generated objects is a technique which greatly improves the realism of their appearance. In this paper, we describe a new method for efficient and fast texture filtering to prevent aliasing during texture mapping. This method, called Fast Footprint MIPmapping, is very flexible and can be adapted to the internal bandwrdth of a graphrcs system. It adopts the prefiltered MIPmap data structure of currently available trilinear MIPmapping implementatrons, but exploits the texels fetched from texture memory in a more optimal manner. Furthermore, like trilinear MIPmapping, fast footprint MIPmapping can easily be realized in hardware. It is sufficient to fetch only eight texels per textured pixel to achieve a significant improvement over classical trilinear MIPmapping.
Hybrid Volume and Polygon Rendering with Cube Hardware
(The Eurographics Association, 1999) Kreeger, Kevin; Kaufman, Arie; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
We present two methods which connect today s polygon graphics hardware accelerators to Cube-5 volume rendering hardware, the successor to Cube4 The proposed methods allow mixing of both opaque and translucent polygons with volumes on PC class machines, while ensuring the correct compositing order of all objects. Both implementations connect the two hardware acceleration subsystems at the frame buffer. One shares a common DRAM buffer and one run-length encodes images of thin slabs of polygonal data and then combines them in the Cube composite buffer In both realizations, we take advantage of the predictable ordered access to frame buffer storage that is utilized by Cube-5 and the rest of the family of volume rendering accelerators based on the Cube design.
Load Balancing for Multi-Projector Rendering Systems
(The Eurographics Association, 1999) Samanta, Rudrajit; Zheng, Jiannan; Funkhouser, Thomas; Li, Kai; Singh, Jaswinder Pal; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
Multi-projector systems are increasingly being used to provide large-scale and high-resolution displays for next-generation interactive 3D graphics applications, including large-scale data visualization, immersive virtual environments, and collaborative design. These systems must include a very high-performance and scalable 3D rendering subsystem in order to generate high-resolution images at real-time frame rates. This paper describes a sort-first parallel rendering system for a scalable display wall system built with a network of PCs, graphics accelerators, and portable projectors. The main challenge is to develop scalable algorithms to partition and assign rendering tasks effectively under the performance and functionality constraints of system area networks, PCs, and commodity 3-D graphics accelerators. We have developed three coarse-grained partitioning algorithms, incorporated them into a working prototype system, and run initial experiments aimed at evaluating algorithmic trade-offs and performance bottlenecks in such a system. Results of our experiments indicate that the coarse-grained characteristics of the sort-first architecture are well suited for constructing a parallel rendering system running on a PC cluster.
A Low-Cost Memory Architecture For PCI-Based Interactive Ray Casting
(The Eurographics Association, 1999) Doggett, Michael; Meißner, Michael; Kanust, Urs; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
In this paper we present a low-cost memory architecture running at 100 MHz which is suited for any PCI-based volume rendering accelerator using the ray-casting approach. Current SDRAM technology, parallel access to all voxels required for trilinear interpolation, a cubic addressing scheme, and a buffering mechanism accommodating memory latency are applied to achieve high frame-rates. A total of four off-the-shelf standard DIMM modules are required enabling up to 9 Hz (averaged over a representative set of views) for datasets of 2563 voxels, using early ray termination as the only algorithmic optimization. The presented memory architecture is a good balance of cost versus feasibility on a standard PC1 card - accepting data replication - and will be used for the VIZARD II ray casting accelerator.
Multiresolution Rendering With Displacement Mapping
(The Eurographics Association, 1999) Gumhold, Stefan; Hüttner, Tobias; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
In this paper, we present for the first time an approach for hardware accelerated displacement mapping. The displaced surface is generated from a 2D displacement map by remeshing a coarse triangle mesh according to the screen projection of the surface The remeshing algorithm is implemented in hardware. Filtered access to the displacement map makes our approach competitive with available view dependent multiresolution techniques. The advantage of displacement mapping is the compact representation. A displacement mapped surface consumes together with all filter levels only a fraction of the storage space needed for a hardware compatible representation of an equivalent triangle mesh. A possible design of the displacement mapping rendering pipeline is proposed. Previously described hardware components are used as often as possible. Our approach can be smoothly integrated into all available graphics application programming interfaces. Most existing graphics applications can be extended to the new feature with marginal effort.
Optimal Depth Buffer for Low-Cost Graphics Hardware
(The Eurographics Association, 1999) Lapidous, Eugene; Jiao, Guofang; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
3D applications using hardware depth buffers for visibility testing are confronted with multiple choices of buffer types, sizes and formats. Some of the options are not exposed through 3D API or may be used by the driver without application s knowledge. As a result, it becomes increasingly difficult to select depth buffer optimal for desired balance between performance and precision. In this paper we provide comparative evaluation of depth precision for main depth buffer types with different size and format combinations. Results indicate that integer storage is preferred for some buffer types, while others achieve maximal depth resolution with floating-point format optimized for known scene parameters. We propose to give 3D applications full control of the depth buffer optimization by supporting multiple storage formats with the same buffer size and exposing them in 3D API. In the search for a unified depth buffer solution, we describe new type of the depth buffer and compare it with other options. Complementary floating-point Z buffer is a combination of a reversed-direction Z buffer and an optimal floating-point storage format. Non-linear mapping and storage format compensate each other s effect on the depth precision; as a result, depth errors become significantly less dependent on the eye-space distance, improving depth resolution by the orders of magnitude in comparison with standard Z buffer. Results show that complementary Z buffer is also superior to inverse W buffer at any storage size. At 16 and 24 bits/pixel, average depth errors of complementary Z buffer remain 2 times larger than for true W buffer utilizing expensive high-precision per-pixel division. However, it provides absolutely best precision at 32 bits/pixel, when errors are limited by floating-point per-vertex input. Results suggest that complementary floating-point Z buffer can be considered as a candidate for replacement of both screen Z and inverse W buffers, at the same time making hardware investment in the true W buffer support less attractive.
Parallel Texture Caching
(The Eurographics Association, 1999) lgehy, Homan; Eldridge, Matthew; Hanrahan, Pat; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
The creation of high-quality images requires new functionality and higher performance in real-time graphics architectures. In terms of functionality, texture mapping has become an integral component of graphics systems, and in terms of performance, parallel techniques are used at all stages of the graphics pipeline. In rasterization, texture caching has become prevalent for reducing texture bandwidth requirements. However, parallel rasterization architectures divide work across multiple functional units, thus potentially decreasing the locality of texture references. For such architectures to scale well, it is necessary to develop efficient parallel texture caching subsystems. We quantify the effects of parallel rasterization on texture locality for a number of rasterization architectures, representing both current commercial products and proposed future architectures. A cycle-accurate simulation of the rasterization system demonstrates the parallel speedup obtained by these systems and quantities inefficiencies due to redundant work, inherent parallel load imbalance, insufftcient memory bandwidth, and resource contention. We find that parallel texture caching works well, and is general enough to work with a wide variety of rasterization architectures.
Texture Shaders
(The Eurographics Association, 1999) McCool, Michael D.; Heidrich, Wolfgang; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
Extensions to the texture-mapping support of the abstract graphics hardware pipeline and the OpenGL API are proposed to better support programmable shading, with a unified interface, on a variety of future graphics accelerator architectures. Our main proposals include better support for texture map coordinate generation and an abstract, programmable model for multitexturing. As motivation, we survey several interactive rendering algorithms that target important visual phenomena. With hardware implementation of programmable multitexturing support, implementations of these effects that currently take multiple passes can be rendered in one pass. The generality of our proposed extensions enable efficient implementation of a wide range of other interactive rendering algorithms. The intermediate level of abstraction of our API proposal enables high-level shader metaprogramming toolkits and relatively straightforward implementations, while hiding the details of multitexturing support that are currently fragmenting OpenGL into incompatible dialects.
TRIANGLECASTER Extensions To 3BTexturing Units For Accelerated Volume Rendering
(The Eurographics Association, 1999) Knittel, Gunter; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
We discuss hardware extensions to 3D-texturing units, which are very small but nevertheless remove some substantial performance limits typically found when using a 3D-texturing unit for volume rendering. The underlying algorithm uses only a slight modification of existing method, which limits negative impacts on application software. In particular, the method speeds up the compositing operation, improves texture cache eflciency and allows for early ray termination and empty space skipping. Early ray termination can not be used in the traditional approach. Simulations show that, depending on data set properties, the performance of readily available, low-cost PC graphics accelerators is already suflcient for real-time volume visualization. Thus, in terms ofperformance, the TRIANGLECASTER-extensions can make dedicated volume rendering accelerators unnecessary.
Z3: An Economical Hardware Technique for High-Quality Antialiasing and Transparency
(The Eurographics Association, 1999) Jouppi, Norman P.; Chang, Chun-Fa; A. Kaufmann and W. Strasser and S. Molnar and B.- O. Schneider
In this paper we present an algorithm for low-cost hardware antialiasing and transparency. This technique keeps a central Z value along with compact floating-point Z gradients in the X and Y dimensions for each fragment within a pixel (hence the name Z3). It uses a small fixed amount of storage per pixel. If the visible complexity of the pixel exceeds the storage space available for the pixel, the minimum number of fragments having the closest Z values are merged. This combines different fragments from the same surface, resulting in both storage and processing efficiency. When operating with opaque surfaces, Z3 can provide superior image quality over sparse supersampling methods that use eight samples per pixel while using storage for only three fragments. Z3 also makes the use of large numbers of samples (e.g., 16) feasible in inexpensive hardware, enabling higher quality images. It is simple to implement because it uses a small fixed number of fragments per pixel. Z3 can also provide order-independent transparency even if many transparent surfaces are present. Moreover, unlike the original A-buffer algorithm it correctly antialiases interpenetrating transparent surfaces because it has three-dimensional Z information within each pixel.

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