EGGH87: Eurographics Workshop on Graphics Hardware 1987

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3D Graphics For Consumer Applications -How Realistic Does it Have to Be?
(The Eurographics Association, 1987) Winser, Paul; Fons Kuijk and Wolfgang Strasser
The design of graphics Ie's for the consumer market has performance limitations imposed by the need to maintain low cost, and must be driven by consideration of the potential applications. The likely requirements for a consumer aimed real time 3D graphics system are stated in terms of performance and rendering techniques, and a research prototype of a 3D display processor is presented. The processor performs polygon drawing with smooth shading, Z buffer, and texture mapping into standard memory components. Limitations of the system and necessary image quality improvements are discussed.
Cellular Architectures and Algorithmsfor Image Synthesis
(The Eurographics Association, 1987) Meriaux, Michel; Fons Kuijk and Wolfgang Strasser
The aim of this paper is to provide some refiexions and partial results about cellular architectures for image synthesis and graphics. As some steps of image synthesis involve a long processing time, quite incompatible with interactivity, a natural solution consists in parallel processing. Though a lot of work has been done about cellular hardware, only a little exists about cellular graphic algorithms and hardware.
Comparison of Two Floatin~Point Arithmetic Unitsfor a Precomputer in a Graphics System forReal Time Simulation
(The Eurographics Association, 1987) Möller, Reinhard; Fons Kuijk and Wolfgang Strasser
This paper compares two realized concepts of floating point units in a visual system for a traffic simulator. The hardware structure of a Transformation Processor is described, with which a set of 1x4 vectors can be floating point multiplied by a 4x4 matrix autonomously in real time. It will be shown, that the speed of graphics computations can be advanced enormously by using specially designed parallel graphics hardware but also requires the elimination of some design constraints given by the available building blocks in VLSI design today.
An Exact Incremental Hidden Surface RemovalAlgorithm
(The Eurographics Association, 1987) Kuijk, A.A.M.; Hagen, P.J. W. ten; Akman, V.; Fons Kuijk and Wolfgang Strasser
This paper describes an incremental Hidden Surface Removal Algorithm (HSRA), developed to be embedded in a new architecture for raster graphics described in [1,7]. The algorithm can be classified as "exact" since it operates in object space, rather than image space. It can be classified as "incremental" because this HSRA is able to support addition, removal and changes on a single object or a group of objects. Thus a firm basis for powerful interaction and animation is established. Due to specially designed data structures for both geometriC objects as well as storage of these objects, the hidden surface removal calculation on a complete scene will have the same time complexity as existing algorithms. However, the effort needed for incremental changes is much less than any other known algorithm. The data structures as well as the algorithm are designed to exploit parallelism in computation.
A Multi-Processor Workstationwith a Logic-Enhanced Distributed Frame Buffer
(The Eurographics Association, 1987) Jansen, Frederik W.; Fons Kuijk and Wolfgang Strasser
A graphics workstation should offer both a wide variety of 20 and 3D realtime display functions as well as a programmable parallel-processing capacity for large processing tasks. A system concept is proposed that meets these requirements by offering a multi-processor configuration with general-purpose programmable processors, enhanced with specific logic that can perform for each node a large number of simple pixel operations in parallel.
A Multiple Application Graphics Integrated CircuitMAGIC II
(The Eurographics Association, 1987) Finch, H.R; Agate, M.; Garel, A.A.; Lister, P.F.; Grimsdale, RL; Fons Kuijk and Wolfgang Strasser
This paper describes the design considerations for a polygon graphics geometry processor subsystem. The architecture for a Multiple Application Graphics Integrated Circuit (MAGIC II) is outlined, and low, medium and high performance system configurations using MAGIC II are discussed.
New Algorithms for Computer Graphics
(The Eurographics Association, 1987) Ovennars, Mark H.; Fons Kuijk and Wolfgang Strasser
"IntroductionThe area of computational geometry deals with the study of algorithms for problems concerning geometric objects like e.g. lines, polygons, circles, etc. in the plane and in higher dimensional space. Since its introduction in 1976 by Shamos the field has developed rapidly and nowadays there are even special conferences and journals devoted to the topic. A list of publications by Edelsbrunner and van Leeuwen [6] collected in 1982 already contained over 650 papers. And this number has rapidly increased since then."
An O(log N) Parallel Time Exact Hidden-LineAlgorithm
(The Eurographics Association, 1987) Dévai, F.; Fons Kuijk and Wolfgang Strasser
"Parallel algorithms are given for the exact solution of the hidden-line problem. Most of the parallel algorithms proposed for visibility problems in the literature give approximate solutions. and thus cannot yield an upper bound on the complexity of the particular problem. The first algorithm proposed here is worth mentioning not only for its simplicity. but also from a practical point of view: a speed up of a factor P is achieved by using P processors. l"";;P"";;N. where N is the number of edges used to describe a polygonal scene. Additionally. the problem of aliasing inherent with approximation methods is avoided.The significance of the second algorithm, which is based on the first one, is mainly on the theoretical level: it is used to establish the parallel complexity of the hidden-line problem. The sequential complexity of this problem has recently been proved to be e(N2). and now we can prove that in the parallel case the problem is in the complexity class NC, Le., it can be solved in time polynomial in logN by using a number of processors polynomial in N, assuming any reasonable model of parallel computation. More particularly, an O(logN) parallel time solution is given which cannot be further improved even if arbitrarily many processors of a concurrent read, exclusive write parallel RAM model are available."
Parallel Subpixel Scanconversion
(The Eurographics Association, 1987) Claussen, Ute; Fons Kuijk and Wolfgang Strasser
"IntroductionComputer graphics and its subsections image processing, image analysis and image generation are known to be a wide field for the application of parallel architectures. While in image processing and analysis the demand for ""real time"" computation is in the center of discussion, it becomes more and more important in the field of image generation, too. Some applications, like sequences of realistic appearing images raise highest demands on algorithm and architecture as well."
Partially Ordered Search Indices in the Organizationof a Fixed Hierarchy
(The Eurographics Association, 1987) Skyttä, Jorma; Takala, Tapio; Fons Kuijk and Wolfgang Strasser
"IntroductionThe mapping of even very advanced algorithms directly to hardware does not typically bring good results as these algorithms are originally designed for sequential processing. However, the power of the modern integration technology lies in its ability to produce high volumes of reasonably complex elements at moderate cost. For utilization of these possibilities the algorithms and data structures already developed must be redesigned for parallel computation."
Pixel-Planes 4: A Summary
(The Eurographics Association, 1987) Eyles, John; Austint, John; Fuchs, Henry; Greer, Trey; Poulton, John; Fons Kuijk and Wolfgang Strasser
We describe the current state of the Pixel-planes research project, whose goal is to develop powerful raster graphics systems for the next generation of workstations, The first full-scale prototype has been in regular use in our department's computer graphics laboratory since its first demonstration at SIGGRAPH '86, more than a year ago, We describe the final hardware configuration of the prototype system, filling in some of the engineering details heretofore unpublished, Next we outline the programming environment for the machine and summarize the major algorithms that have been developed, Finally we discuss our progress towards a new generation of the Pixel-planes architecture, Pixelplanes 5.
Ray Tracing Rational B-Spline Patches in VLSI
(The Eurographics Association, 1987) Schneider, Bengt-Olaf; Fons Kuijk and Wolfgang Strasser
Rational B-spline surfaces make it possible to merge the concepts of freeform surfaces and that of surfaces described by rational polynomials especially conic sections. For ray tracing it is crucial to determine the intersection between ray and object. Therefore an algorithm is developed that is suitable for a VLSI implementation. Some alternatives for the implementation of this algorithm are presented and discussed. The paper concludes with a discussion of some problems and possible further developments.
Reconstructing Solids from Tomographic Scans --The PARCUM II System-·
(The Eurographics Association, 1987) Jackèl, D.; Fons Kuijk and Wolfgang Strasser
The computer-aided design of mechanical parts is supported by sophisticated geometric modelers and visualized by high-performance raster graphics systems allowing for a realistic display. The geometric modeler accepts the designer's inputs and converts them into a 3D model. In general, the designer has total control of the object description defining his design. But in contrast, the situation is different when dealing with existing physical Objects, e.g. natural objects such as the human body, for which an explicit 3D model is required. For instance, in many applications the input information is a sequence of 2D tomographic scans. In this case the task is to combine both the interactive CAD-mode of construction as well as the scan-based mode of reconstruction in an integrated system, such that an unique 3D object representation is achieved and can be supported by hardware efficiently. Here we describe a cellular space representation scheme which is supported by a voxel-oriented graphics system --the PARCUM II System--.
A Two-Dimensional Frame Buffer Processor
(The Eurographics Association, 1987) Kaufman, Arie; Fons Kuijk and Wolfgang Strasser
The two-dimensional Frame Buffer Processor (FBP) is part of a proposed raster graphics computer architecture. It is a hardware-oriented organisation of a variation of a bitblt engine with a much richer repertoire. In addition, the FBP gives support to window management, transformations, and assists in some image operations ordinarily performed in software. The introduction of the FBP as a co-processor to geometry and video processors would increase efficiency and speed of graphics systems and bitmap workstations. A special skewed frame-buffer organisation, which allows parallel memory access, further improves system performance.
A Vector-like Architecture for Raster Graphics
(The Eurographics Association, 1987) Akman, Varol; Hagen, Paul ten; Kuijk, Fons; Fons Kuijk and Wolfgang Strasser
Raster graphics, while good at achieving realistic and cost-effective image generation, lacks useful (e.g. high-level) and fast (e.g. almost real-time) interaction facilities. One may try to speed up the entire classical image generation pipeline using much processing power but this would clearly lessen the advantages of raster workstations as popular, relatively inexpensive devices. This paper continues our work in restructuring the functional model (first formulated by Ingrid Carlbom) for high-performance architectures. Central to our approach is a visible concern about the underlying data structures used to represent the geometric objects. This originates from the conviction that only through careful design of appropriate graphics data structures and algorithms one can profitably map software tasks into hardware, specifically VLSI. Here we elaborate on a novel object description scheme called "pattern representation" and its envisioned usage. Our work is decidedly in contrast with several current research efforts in the area of graphics hardware where it is commonplace to simply put several processors into a cooperative effort to share the total burden, with each processor taking responsibility for part of the work.
VLSI Drawing Processor Utilizing Multiple ParallelScan-Line Processors
(The Eurographics Association, 1987) Denault, Damian; Ryherd, Eric; Torborg, John; Fons Kuijk and Wolfgang Strasser
In a typical graphics system, a single drawing processor is used to perform pixel level drawing operations, one pixel at a time. A VLSI based drawing processor and image memory controller is presented which takes advantage of scan-line partitioning of many graphics operations. A four processor implementation is described which operates on four scan-lines in parallel to achieve near real-time shading performance for complex objects. Drawing processor commands are provided for points, vectors, triangles, rectangles, block pixel moves, and image transfers. Vectors and triangles can be drawn with shading and depth buffering. The chips also incorporate integral vector and area pattern registers, and support translucency. The drawing processor chips directly interface to the image memory RAMs without any external buffers, registers, caches, or control logic, allowing a high performance system to be configured simply and cost effectively. These chips are implemented in the GX4000 high performance workstation graphics system which is capable of rendering close to 200,000 shaded and depth-buffered 100 pixel polygons per second and over 34,000 shaded and depth-buffered 1000 pixel polygons per second.

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