EGGH91: Eurographics Workshop on Graphics Hardware 1991

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https://diglib.eg.org/handle/10.2312/344

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The Flipping Cube: A Device for Rotating 3D Rasters
(The Eurographics Association, 1991) Yagel, Roni; A. Kaufman
Driven by the prospect of three-dimensional rasters as a primary vehicle for future 3D graphics and volumetric imaging, this paper introduces an architecture for real-time rendering of high-resolution volumetric images. The Flipping Cube Architectureutilizes parallel memory organization and a unique data orientation schemein order to support contention free access to viewing rays."
An Architecture for a High Performance Rendering Engine
(The Eurographics Association, 1991) Ackermann, Hans-Josef; Hornung, Christoph; A. Kaufman
We present an architecture for a high-performance programmable rendering engine.This chip or chip-set will be able to deliver one Gouraud-shaded, z-buffered, texturemodulated and alpha-blended pixel every clock cycle. Focus of the paper is the derivation of the architecture of the pixel processing block from the applied algorithms."
Space Partitioning for Mapping RadiosityComputations onto a Pipelined Parallel Architecture (II)
(The Eurographics Association, 1991) Shen, L.S.; Laarakker, F.A.J.; Deprettere, E.; A. Kaufman
A new space partitioning technique is elaborated. In part I of the paper [3], we proposed a shell-like structure which is to be superimposed on a uniform grid data structure and is adaptive to the local environment seen by a bundle of rays. Here we extend this segmentation by embedding it in a static partitioning which is determined by low resolution ray casting. This partitioning is useful in achieving a balanced computation while mapping it onto a pipelined parallel architecture. Moreover, a run-time control of workloads is applied during a subsequent high resolution ray casting so as to adjust low resolution partitioning. The technique has been tested on practical and randomly generated scenes. The performance evaluation of a pipelined parallel architecture has been done by queueing network simulation. Promising results have been obtained.
Accurate Scanconversion of Triangulated Surfaces
(The Eurographics Association, 1991) Rossignac, Jarek R.; A. Kaufman
Scanconverting a planar face produces depth-values for pixels totally or partly covered by the projection of that face. State-of-the-art hardware-supported scanconversion techniques use sub pixel adjustment and extended precision calculations to achieve an acceptable depth-accuracy despite numeric round-off errors. Unfortunately, this depth-accuracy only holds for the interior pixels of the face. During the scanconversion of the boundaries of polyhedral solids or of the tesselations of curved surfaces, significantly larger depth-errors may occur at pixels traversed by the projection of the bounding edges. These errors are due to the use of the wrong surface equations resulting from an erroneous classification of pixels with respect to the projections of faces. They may lead to logical mistakes of serious consequences for hidden-surface removal and for solid-modeling applications. To address this problem, a new scanconversion technique is presented, which exploits surface data and face/face adjacency information to infer face-projections. For simplicity, the exposition is confined to triangular faces of manifolds, where each edge is adjacent to two triangles. At pixels covered by the projection of an edge, the surface depth computed in the standard manner is compared to the depth of the surface supporting the adjacent triangle. Pixel classification is obtained by taking into account the result of this comparison and the orientations of both faces.
The I.M.O.G.E.N .E. Machine: Some Hardware Elements
(The Eurographics Association, 1991) Lefevere, V.; Karpf, S.; Chaillou, C.; Meriaux, M.; A. Kaufman
The goal of the I.M.O.G.E.N.E. project is to define a real time graphics system. We focus on true real time display, images being computed at frame rate, i.e 50 (or 60) times a second. The I.M.O.G.E.N.E. machine uses no frame buffer. We use a massive object parallelism; the graphics module is made of a large number of object-processors, each one handling one graphics primitive at pixel rate in raster-scan order. Shading computations are made in a deferred shading processor using Phong's method. After a brief presentation of Object-Oriented Architectures,we present new details about the hardware implementation of our Object Processors, and describe for the first time the shading processor.
Dynamic Load Balancing within a High PerformanceGraphics System
(The Eurographics Association, 1991) Selzer, Harald; A. Kaufman
Interactive 3D graphics applications require significant arithmetic processing to meet the ever-inreasing desire for higher image complexity and higher resolution in displayed images. This paper describes a graphics processor architecture with a high degree of parallelismconnected to a distributed frame buffer. The architecture can be configured with an arbitrary number of identical, high level programmable processors operating in parallel.Within the architecture an automatic load balancing mechanism is presented whichdistributes the processing load between geometry and rendering section. After the unique features of the architecture are described the load balancing mechanismis analyzed and the increase of performance is demonstrated."
Hardware Outline Character Rasterization
(The Eurographics Association, 1991) Morgan, Marc; Hersch, Roger D.; A. Kaufman
This paper presents the design and implementation of an application specific integrated circuit (ASIC) for real-time rasterization of characters described by their outline based on vertical scan-conversion and flag fill algorithms. The chip acts as a coprocessor which rasterizes outline fonts given by Bezier splines and straight line segments. It generates high quality fonts at a rate 30 times higher than the equivalent assembly language code on a 16 MHz M68020.
Silicon Compilers for Graphics Hardware Design
(The Eurographics Association, 1991) Renz, Oliver; Groene, Alwin; A. Kaufman
Experiences with the realization of an object processor using a silicon compiler will be described. Object processors are parts of the object oriented display processor architecture PROOF (Pipeline for Rendering in an Object Oriented Framework; [9] and [8]). Placed in an object processor pipeline the object processors perform the scan conversion, the interpolation of the depth values and the normal vectors of the primitive objects of a scene to be rendered. The suitability of the silicon compiler GENESIL^ 1 for the development of graphics hardware will be examined using the object processor as an example.
The Conveyor - an Interconnection Device for ParallelVolumetric Transformations
(The Eurographics Association, 1991) Cohen, Daniel; Bakalash, Reuven; A. Kaufman
This paper presents the conveyor, an interconnection device which operates on a 3D skewed memory space and provides the capability of parallel volumetrictransformation. The special concept of the conveyor, its design and implementationare discussed."
XInPosse: Structural Simulation for Graphics Hardware
(The Eurographics Association, 1991) Guravage, M.A.; Blake, E.H.; Kuijk, A.A.M.; A. Kaufman
A structural simulator is used both to test hardware and to visualizesoftware that should run on that hardware. In a layered set of graphical hardwaresimulators, a structural simulator bridges the gap between hardware fidelity on theone side and sufficient performance to visualize graphics algorithms on the other. Essential design requirements were code extensibility and reusability. In order to achieve this, object-oriented methods were adopted. Important design criteria for graphical hardware simulators at this level are that both the exact digital state of the hardware and the graphical output be visualized interactively. The experience with using the XInPosse simulator is presented and analysed. XInPosse simulates a large systolicarray in custom VLSI for second order interpolation; in this case to produce shadedscanlines. XInPosse provides the user with a means of tracing commands within thearray while interactively setting breakpoints and displaying processors of particularinterest. It verified that the hardware could execute the graphics algorithms correctlyand that the limitations on numerical accuracy and range were graphically acceptable.An unexpected use was to facilitate communication between chip designers andthe graphics researchers. Problems in the documentation of the hardware and workarounds for hardware ""bugs"" were found more easily through the common reference frame provided by the simulator. It is the intention of the authors to use the modularity provided by the object-oriented design to produce a toolkit for building graphical hardware simulators."
Issues and Directions for Graphics Hardware Accelerators
(The Eurographics Association, 1991) Akeley, Kurt; A. Kaufman
Testing Geometric Primitive Shaders
(The Eurographics Association, 1991) Dunnett, G. J.; White, M.; Lister, P. F.; Grimsdale, R. L.; A. Kaufman
We present a design and test strategy for Geometric Primitive Shadersintegratedcircuits which perform rasterisation of primitives such as vectors and triangles.The design strategy proceeds through various levels of detail, and we describethe need for testing as the design advances. A suitable set of test are given for a typicalshader. Our experiences in applying the strategy to a real device are discussed,together with the tests which we devised, and practical compromises which we had to make."

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